Download Product Beleif file:

Flexible QC-LDPC Decoder IP for NR-5G v1.1

Contact for More Information: info@curvtech.com

The LDPC Decoder is a highly optimized IP core intended to work with Xilinx FPGAs or ASIC implementation. The LDPC Decoder benefits from a flexible structure to fit almost all Quasi-Cyclic (QC) LDPC codes in arbitrary code length and code rate configuration by passing different parameters and a little modification to Verilog codes.

NR-5G LDPC code is designed very flexible to be used with many code length and code rate configurations, and the maximum parallel size is up to 384. The NR-5G LDPC Decoder IP is made as an example and described below.

Features

  • 5G NR LDPC codes decoder support both base graphs and all Zc sizes and code rate configs
  • Throughput up to 2.071Gbps @8 iterations @200MHz on Xilinx Virtex UltraScale FPGA VCU095

Overview

The LDPC Decoder benefits from a flexible structure. Custom and standardized LDPC codes are supported through the ability to specify the parity check matrix through modification of H matrix ROM and the barrel shifter module. A block diagram of the LDPC Decoder core is shown in Figure 1.

Figure 1: LDPC Decoder Core Block Diagram

Feature Summary

The LDPC Decoder core is a highly flexible soft-decision LDPC decoder with the following features:

  • Row-Message-Passing layered decoding algorithm to speed up iteration convergence
  • Normalize Min-Sum decoding algorithm,¬†Normalization Factor is 0.75.
  • Highly parallel structure to supply high throughput and low latency performance (¬†384 parallel Units for NR-5G.
  • High configurable codes:¬†A range of quasi-cyclic codes can be supported by modifying the H matrix ROM and barrel shifter modules.
  • Flexibility to do on-the-fly running blcok by block
  • Input 6-bit width LLRs are always organized in parallel of 16, if LLR length is not multiples of 16, zeroes padding should be attached to the last input cycle.
  • Output Hard-Decision bits are always organized in parallel of 16 too. Also, zeroes padding is attached if necessary.
  • Number of iteration 1~64
  • Early Stop criteriaStop criteria can be configured to be one of the three: a) Parity Check passes; b) Parity Check passes in tow continuous iteration cycles; c) Maximum iteration number is reached.

Resource Utilization

Implemented on Xilinx Virtex UltraScale VCU095. LUT is 6-input, RAM size is 36kbits.

 

Parallelism LUT FF RAM DSP48
384 106951 62062 122.5 0

Deliverables

  • Verilog RTL source code or synthesized netlist
  • Verilog HDL simulation models and testbench with random regression environment for VCS
  • Bit-accurate Matlab, C or C++ golden model
  • Comprehensive documentation

 

Contact for More Information: info@curvtech.com